As the semiconductor industry develop towards smaller and faster devices, the lateral feature size (e.g., gate length) and feature depth (e.g., source/drain junction depth) of semiconductor devices become gradually smaller, and operation speed of the devices become faster and faster. To suppress short-channel effect, the source/drain and source/drain extension regions are required to become shallower. The source/drain junction depth of semiconductor devices is required to be less than 30 nm according to current processing technologies. Ultra-shallow junctions for future technology node can become less than 15 nm.
In back-end of line (BEOL) processing of semiconductor devices, source and drain need to be led out by filling vias or contact holes with metal (e.g., tungsten), so that metal interconnect can be formed subsequently to connect individual devices. As known in this field, the vias act as electrical pathways between the BOEL metal layers (e.g., copper) and source/drain and gate electrodes of the devices, and are typically formed by etching holes or trenches in a dielectric layer and filling the holes or trenches with metal. As semiconductor device sizes become smaller and smaller, the vias also become smaller and smaller, and for the metal in the vias, the ratio of the length along the direction of current flow to cross-sectional area perpendicular to the direction of current flow can become larger, resulting in the resistance of the metal filling the vias to become larger. Furthermore, this conducting material in the vias and the silicon dioxide in the dielectric layer are required to have a good interface and good adhesion properties, and the conducting material should not cause structural damage of the dielectric material. Moreover, contact resistance between the metal in the vias and metal silicide source/drain contacts can become larger. Because the resistance of the metal in the vias and the contact resistance can become larger, device operating efficiency can be affected. Also, as the vias become smaller and smaller, their aspect ratios become larger, making it more and more difficult to fill them with metal, and more challenging to maintain metal filling consistency.
In order to minimize the resistance of the metal in the vias and the contact resistance, and to insure metal filling consistency among vias of different aspect ratios, low resistivity metal materials such as tungsten is usually selected for via filling. Tungsten, however, can damage silicon dioxide or silicides when contacting the silicon dioxide dielectric layer or silicide source/drain contacts, and can even react with the silicon under the silicides. Thus, a barrier layer (e.g., titanium nitride TiN) is considered to be placed between tungsten and silicon dioxide or silicides. Such a barrier layer, however, would have higher resistance than tungsten. Furthermore, the addition of the barrier layer can cause the tungsten in the vias to be come even smaller, and the resistance of the metal in the vias to be even larger, thereby further increasing the resistance of the vias.